Parallel 4-bit Adder
4bit adder

Parallel 4-bit Adder

Parallel 4-bit Adder:

The parallel adder is the most important element used in arithmetic operations of many processors. With the rising popularity of mobile devices, low power consumption and high performance integrated circuits has been the target of recent research. However, the two design criteria are often in conflict and that improving one particular aspect of the design constrains the other. Design for low power consumption and high performance is further complicated by the myriad of factors that are introduced through the development life cycle of the digital processor. Development is based on a five-tier model: System Integration, Algorithm Selection, Architectural Design, Circuit/Logic Design, and finally, Process Technology. This project shall focus on the Circuit/Logic Design level. Design at this level is restricted by the given process technology.
The objective of this project is to design a 4-bit adder that is optimized for low power consumption. However, it should be noted that power dissipation optimization should be applied throughout the development process from system-level to process-level while realizing that performance is still essential. In reality, it is very important to know the power distribution within a processor and optimize the parts of blocks consuming an important fraction of the power. In the case of this report, the process technology and circuit/logic design is under the control of the designer. The other levels are acknowledged but will be considered negligible in the power analysis of this report with respect to the target application. It is assumed that as long as power consumption by the 4-bit adder falls below the constraints of the target application within a certain fraction, therefore the design objectives are met.
The 4-bit adder design is completed in the following manner: the target application is first chosen; next, the adder architecture is selected for its appropriateness for that application. The architecture is analyzed by tracing the worst-case path for power dissipation and sections of the design are abstracted for optimization. Finally, the schematic design of the adder is translated into layout and its performance metrics are compared with those from the schematic as well as the target application.

Leave a Reply

Close Menu
×
×

Cart