To design a full adder with a majority gate to reduce power and increase performance.
Various static CMOS logic styles have been used to implement low power and high performance 1 bit full adder cells like FA24T, CPL, and DPL etc. But these CMOS logic styles are designed with many transistors with consumes more power and reduces the performance of the system.
Introducing an efficient method for implementing majority gates, which is more high-performance and efficient, and utilize it for implementing the Cout generator part of our proposed Full Adders.
The promotions in battery technology have not occurred as fast as the promotions in electronic devices. Therefore, the designers are confronted with more limitations such as high speed, high throughput and together with consuming as low power as possible.
In electronics, an adder or summer is a digital circuit that performs addition of numbers. In modern computers adders reside in the arithmetic logic unit (ALU) where other operations are performed. Although adders can be constructed for many numerical representations, such as Binary-coded decimal or excess-3, the most common adders operate on binary umbers. In cases where two’s complement or one’s complement s being used to represent negative numbers, it is trivial to modify an adder into an adder-subs tractor. Other signed number representations require a more complex adder. A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in (in theory from a past addition).