MEASUREMENT AND EVALUATION OF POWER ANALYSIS ATTACKS ON ASYNCHRONOUS S-BOX
This paper demonstrates the hardware implementation of a recently proposed low-power asynchronous Advanced Encryption Standard substitution box (S-Box) design that is capable of being resistant to side channel attack (SCA). A specified SCA standard evaluation field-programmable gate array (FPGA) board is used to implement both synchronous and asynchronous S-Box designs. This asynchronous S-Box is based on self-time logic referred to as null convention logic (NCL), which supports a few beneficial properties for resisting SCAs: clock free, dual-rail encoding, and monotonic transitions. These beneficial properties make it difficult for an attacker to decipher secret keys embedded within the cryptographic circuit of the FPGA board. Comparisons on the resistance to SCAs of both the original and proposed S-Box design are presented, using differential power analysis (DPA) and correlation power analysis (CPA) attacks. The power measurement results showed that the NCL S-Box have lower total power consumption than the original and was effective against DPA and CPA attacks.
To provide the error detection, recognizing that previously proposed schemes are not well suited to compact implementations, it is proposed to adopt a hybrid approach consisting of parity codes in combination with partial circuit redundancy. For compact ASIC implementations, taking such an approach gives a better ability to detect faults than simple parity codes, with less area cost than proposed schemes which use full hardware redundancy
EXISTING SYSTEM ALGORITHM:
Compact AES hardware implementations are typically iterative designs based on one-round or quarter-round loop architectures, with the application of design techniques for hardware resource sharing such as the merging of the encryption and decryption data paths and the reuse of components between the data path and key expander.